1. Field of the Invention
The present invention relates to a line memory which has a relatively small capacity and can execute a completely synchronized write operation and read operation.
2. Description of Related Art
FIG. 27 shows a circuit configuration of a conventional line memory. This line memory comprises one memory cell array 10. The line memory also comprises four data registers 12, 14, 16 and 18 each of which has a register for one line. These data registers 12-18 are connected to the memory cell array 10 via bit lines BL. This line memory also has a data sub-register 20 which has a register for one line. This line memory further comprises an X decoder 22, an X predecoder 24, an address counter 26, a read/write controller 28, an input buffer 30 and an output buffer 32. The X decoder 22 is connected to the memory cell array 10 via the word line WL. The read/write controller 28 generates a read control signal RC and a write control signal WC to control the data registers 12-18. These components are synchronized with common clock signals.
The write operation is executed as follows. At first, write data WD is input from the input port Din to the input buffer 30. The write data WD, driven by the input buffer 30, is sequentially written to the data sub-register 20. After one line of data is written to the data sub-register 20, the next write data is written to the first data register 12. After one line of data is written to the first data register 12, the address counter 26 generates an X address signal XA. This X address signal is sent to the X decoder 26 via the X predecoder 24 and is decoded by the X decoder 26. By the decoded X address signal, the word line WL is activated. Then by the activation of the write control signal WC, all the data of the first data register 12 is transferred in batch to the memory cell array 10 via the bit line BL. During this time, the next write data is sequentially written to the second data register 14. After writing the data to the second data register 14, the written data is transferred in batch to the memory cell array 10, just like the data of the first data register 12, and writing to the first data register 12 is executed during this time. By repeating these operations, a continuous write operation is implemented.
Read operation is executed as follows. At first, the data of the data sub-register 20 is sequentially output to the output buffer 32. The read data RD of the output buffer 32 is output to the output port Dout. During this time, the X address signal generated by the address counter 26 is decoded by the X decoder 22 and the word line is activated by the decoded X address signal. Then the read control signal RC is generated, and one line of data of the memory cell array 10 is transferred in batch to the third data register 16 via the bit line. After reading the data sub-register 20 completes, and the third data register 16 is read. During this time, a data transfer to the fourth data register 18 is executed, just like the data of the third data register 16. By repeating these operations, a continuous read operation is implemented.
Therefore according to the line memory shown in FIG. 27, a line memory operation where a read operation and a write operation are completely a synchronized is possible. With this line memory, line memory operation in accordance with a specification where functions are partially restricted as shown in the timing chart in FIG. 28 is also possible. In FIG. 28, CLK shows a clock signal and RST shows a reset signal. A read operation and a write operation of data are executed synchronizing with the cycle unit of the clock signal CLK. As FIG. 28 shows, this line memory reads the data R0 from the address No.0 of the memory cell array 10 at the first clock cycle CLK0. At the next clock cycle CLK1, data W0 is written to the address No.0, and data R1 is also read from the address No.1. At the next clock cycle CLK2, data W1 is written to the address No.1, and the data R2 is also read from the address No.2. At the next clock cycle CLK3, data W2 is written to the address No.2, and data R3 is also read from the address No.3. In this way, at one cycle after the read operation from a memory cell at a predetermined address of the memory cell array 10, a write operation is executed to the memory cell at this address, and a read operation is executed to a memory cell at another address.
However, if the circuit configuration shown in FIG. 27 is used to configure a small capacity line memory with a specification where functions are restricted as shown in FIG. 28, the layout area of the data register, data sub-register and read/write controller becomes larger than the layout area of the memory cell array, which makes it difficult to decrease the chip size.